1. Field of the Invention
The present invention relates to semiconductor electronic devices and fabrication methods, and, more particularly, to silicided structures in silicon devices.
2. Description of the Related Art
Large scale integrated silicon circuits have become so dense that a single chip may contain several million transistors, and economic pressure indicates further increases in packing density and downscaling of feature sizes. As MOS technology is scaled down to below one micron, the use of silicided source and drain junctions is essential to reduce the series resistance of the diffused regions, and titanium silicide has become a preferred approach. Indeed, titanium silicide typically provides a sheet resistance of about 1.OMEGA./.quadrature. as compared to typical n.sup.+ junction sheet resistance of about 20.OMEGA./.quadrature. and p.sup.+ junction sheet resistance of about 100.OMEGA./.quadrature.; see, for example. C. Lau et al. Titanium Disilicide Self-Aligned Source/Drain+Gate Technology, 1982 IEEE IEDM Tech. Digest 714 and M. Alperin et al, Development of the Self-Aligned Titanium Silicide Process for VLSI Applications, 32 IEEE Tr. Elec. Dev. 141 (1985). But then the contact resistance of a metal line to a source or drain junction is the sum of the metal-to-silicide contact resistance plus the silicide-to-junction contact resistance.
Further, the series resistance contributed by a metal to junction contact increases more rapidly than other resistance components: the contact resistance scales roughly as the inverse square of the feature size for small contacts; see R. Dennard et al, Design of Ion-Implanted MOSFET's with Very Small Physical Dimensions, 9 IEEE J. S. S. Cir. 256 (1974) and W. Loh et al, 2-D Simulations for Accurate Extraction of the Specific Contact Resistivity from Contact Resistance Data, 1985 IEEE IEDM Tech. Dig. 586. That is, the contact resistance is the specific contact resistivity (.OMEGA.-cm.sup.2) divided by the contact area (cm.sup.2), and the specific contact resistivity is area independent (if edge effects are negligible) and theoretically can be approximated for degenerately doped silicon as: ##EQU1## with .phi. the metal-silicon barrier height, N the doping concentration, m the carrier effective mass, and .epsilon. the dielectric permittivity of silicon. As feature size is scaled to below one micron, the metal to junction contact resistance for silicided junctions becomes too large for effective circuit operation due to the high specific contact resistivity of the silicide-to-silicon interface for boron-doped junctions. RC time constants become too long and voltage drops in propagating signals become too great.
Thus there is a problem of high specific contact resistivity in known silicided source and drain junctions as feature size is scaled down.
As feature size is scaled to below one micron, the use of doped polysilicon lines for interconnections becomes impractical due to the high resistivity of doped polysilicon. One approach is to use silicided polysilicon (polycide) lines to lower the sheet resistance. Typically, a layer of polysilicon is deposited and a layer of silicide formed on top, either by deposition of silicide or deposition of metal followed by a silicidation reaction; the polysilicon prevents silicidation of the junctions or moats. The layers are patterned and etched to form the silicided polysilicon lines; however, fine line patterning is difficult because the silicide has a rough surface and silicides are similar to other metals and difficult to selectively etch.
Thus the use of self-aligned titanium silicide technology is essential to the fabrication of submicron very large scale integrated silicon circuits; both the polysilicon lines and the junctions or moats are silicided at the same time to provide highly conductive interconnects. However, the problem of high specific contact resistivity in known source and drain junctions remains.